Answer by Nate Eldredge for Partial reordering of C++11 atomics on Aarch64
I asked the same question in For purposes of ordering, is atomic read-modify-write one operation or two?, not knowing that it was a duplicate.You're right that this means another load or store can be...
View ArticleAnswer by Tsyvarev for Partial reordering of C++11 atomics on Aarch64
Looks like you are right. At least, very similar bug for gcc has been accepted and fixed.They provide this code:.L2: ldaxr w1, [x0] ; load-acquire (__sync_fetch_and_add) add w1, w1, 1 stlxr w2, w1,...
View ArticlePartial reordering of C++11 atomics on Aarch64
I was looking at the compiler output of rmw atomics from gcc and noticed something odd - on Aarch64, rmw operations such as fetch_add can be partially reordered with relaxed loads.On Aarch64, the...
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